1. Field of the Invention
The invention is related to an active device, and in particular to an active device which has an oxide semiconductor layer.
2. Description of Related Art
Among various flat panel displays (FPDs), thin film transistor liquid crystal display (TFT-LCD) characterized by great space utilization, low power consumption, non-radiation, and low electromagnetic interference win popularity with consumers. In general, the TFT-LCD is mainly assembled by an active array substrate, a color filter substrate, and a liquid crystal (LC) layer sandwiched between the two substrates. The active array substrate has an active region and a peripheral circuit region. The active array is located within the active region and a driving circuit is located within the peripheral circuit region.
Taking the driving circuit located within the peripheral circuit region as an example, thin film transistors having a high ratio of channel width/channel length (W/L) are commonly used. In general, the current (Ion) of the TFT when being turned on is directly proportional to the ratio of width/length (W/L) of the channel, and it satisfies the following formula:Ion=U*W/L(VG−Vth)VD, wherein U is carrier mobility, W is channel width, L is channel length, VG is gate voltage, Vth is threshold voltage, and VD is drain voltage. As known from the above formula, the current (Ion) is increased by increasing the ratio of channel width/channel length (W/L). However, the increase in channel width usually affects the layout area to significantly increase. In order to reduce the layout area of the TFT, sources and drains are alternately arranged to increase the ratio of the channel width/channel length (W/L).
FIG. 1A is a schematic top view of a conventional active array substrate with multiple pairs of sources and drains disposed thereon. FIG. 1B is schematic view of the TFT taken along a sectional line A-A′ depicted in FIG. 1A. Referring to FIG. 1A and FIG. 1B, the conventional TFT 100 is fabricated on a substrate 110 and includes a gate 120, a gate insulator layer 130, a semiconductor layer 140, an etch stop layer 150, a source 160 and a drain 170. The gate 120 is disposed on the substrate 110, while the gate insulator layer 130 is disposed on the substrate 110 to cover the gate 120. The semiconductor layer 140 is disposed on the gate insulator layer 130 over the gate 120. The etch stop layer 150 is disposed on the semiconductor layer 140. The source 160 and the drain 170 are disposed on the etch stop layer 150 and portions of the semiconductor 140, and the source 160 and the drain 170 are electrically isolated.
As shown in FIG. 1A, a zigzag trench Z is formed between the source 160 and the drain 170. Both the gate 120 and the semiconductor layer 140 extend along the zigzag trench Z, wherein the width WG of the gate 120 is greater the width WZ of the zigzag trench Z and the width WS of the semiconductor layer 140 is greater than the width WG of the gate 120. Moreover, the gate 120 has a plurality of stripe gaps GG, the semiconductor layer 140 has a plurality of stripe gaps GS, and the width of GS is smaller than the width of GG.
Though the TFT 100 described in FIG. 1A and FIG. 1B already has a rather high ratio of channel width/channel length (W/L), along with the increasingly popularity of the slim border design of the FPDs, the layout area of the TFT 100 is required to further reduce. Accordingly, how to further reduce the required layout area of the TFT 100 under the condition of without reducing the ratio of channel width/channel length (W/L) has become the major development trend.